1. Field of the Invention
The present invention relates to clock generation, application and control, especially to a clock generator, a communication device and a sequential clock gating circuit capable of maintaining a cycle number relation between output clocks.
2. Description of Related Art
In a general Ethernet communication system, two link partners will act as a master and a slave respectively according to a predetermined rule. Each of the master and slave has a clock generator while the two clock generators work independently. As a result, their generated clocks have no constant correlation and usually differ from each other. However, in consideration of that the master and slave must be able to process signals from each other for communication, the clock generator of the slave should recover a master transmission clock according to a received master transmission signal, then generate a slave reception clock similar to or correlating with the master transmission clock, and then set a slave transmission clock in accordance with the slave reception clock; afterwards, the clock generator of the master should recover the slave transmission clock according to a received slave transmission signal, and then generate a master reception clock similar to or correlating with the slave transmission clock. Through the above operation, both parties are able to transmit and receive signals on the basis of a common clock.
Generally, during the process of generating the aforementioned slave or master reception clock, the slave or master will generate plural clocks of the same frequency but different phases through its clock generator, and then choose one of the plural clocks as the reception clock with a timing recovery technique. In order to save power, some Ethernet standard (e.g., IEEE 802.3az Energy Efficient Ethernet (EEE) standard) requires that the two link partners should turn off some heavily power-consuming component (e.g., some component of a physical layer circuit) when entering EEE mode without packet transmission/reception demands, and should come back to a normal mode from EEE mode within a predetermined time interval when detecting packet transmission/reception demands. The predetermined time interval is 20.5 μs for a device operating at 100 Megabit/s transmission rate, and 16.5 μs for a device operating at 1 Gigabit/s transmission rate.
In light of the above, regarding devices operating at 1 Gigabit/s transmission rate, the current Ethernet linking technique makes two link partners store the parameters about clock relation after establishing the link with appropriate clocks and makes the two link partners keep their clock generators working when entering EEE mode in order to comply with EEE standard, so that the two link partners will be able to leave EEE mode and come alive within the aforementioned predetermined time interval. However, the clock generator of an Ethernet device normally consumes a lot of power, so if the clock generator keeps working under EEE mode, the power-saving efficiency will be disappointed; but if the clock generator is turned off under EEE mode and turned on when leaving EEE mode, in view of that the clock generator may output wrong clocks (e.g., clock glitch) when being turned off and/or turned on or the clock relation may change after the clock generator restarted, the two link partners will need a lot of time to calibrate or rebuild the clock relation and therefore be unable to come back to normal operation within the said time interval of EEE standard.
Therefore, this industry needs a technique capable of tackling clock glitch and maintaining the relation between plural clocks when the clock generator generating the plural clocks is turned off and then turned on.
People who are interested in the prior art may refer to Applicant's US patent application with the application Ser. No. 13/793,604.